1. Field of the Invention
The present invention relates in general to a input buffer of semi conductor memory device, and more particularly to input buffer of memory device for reducing current consumption in standby mode in which current to be consumed in an input buffer is interrupted when the input buffer is not operated. The present invention is applicable to all elements employing a packet protocol, such as a rambus, a synchronous link, etc..
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional high-speed device and FIGS. 2a to 2e are timing diagrams of signals transferred between a master 10 and slaves 20.sub.-- 0-20.sub.-- i in FIG. 1.
Conventionally, at the same time that the master 10 transfers data to the slaves 20.sub.-- 0-20.sub.-- i through a bus, it sends a flag signal as shown in FIG. 2c to indicate the data transfer through the bus. In this case, the slaves 20.sub.-- 0-20.sub.-- i receive the first data on the bus when they buffer the flag signal, thereby making it impossible to control input buffers of the slaves 20.sub.-- 0-20.sub.-- i using the flag signal. For this reason, a standby mode signal Stby as shown in FIG. 2d is used to inform the slaves 20.sub.-- 0-20.sub.-- i of a standby mode. The standby mode signal Stby is disabled earlier than the flag signal to make the bus input possible. Also, after the bus input is completed, the standby mode signal Stby is enabled to allow the slaves 20.sub.-- 0-20.sub.-- i to enter the standby mode. As a result, there is conventionally required a time margin between the flag signal and the standby mode signal Stby. Further, the number of control signals is increased in that the standby mode signal Stby is required in addition to the flag signal to control the standby mode. Moreover, standby mode signal input buffers (standby mode detection input buffers) in the slaves 20.sub.-- 0-20.sub.-- i must continuously be operated to recognize a time point where the standby mode signal Stby from the master 10 is received. In result, even when the slaves 20.sub.-- 0-20.sub.-- i are in the standby mode, the standby mode detection input buffers are continuously operated, resulting in continuous power consumption.
FIG. 3 is a block diagram illustrating the construction of a bus input buffer and a standby mode detection input buffer in each of the slaves 20.sub.-- 0-20.sub.-- i in FIG. 1. In this drawing, the bus input buffer is designated by the reference numeral 30 and the standby mode detection input buffer is designated by the reference numeral 31. The standby mode detection input buffer 31 is adapted to inform the bus input buffer 30 of the standby mode in response to a clock signal and the standby mode signal Stby. The bus input buffer 30 is adapted to buffer an input bus signal BUS0:j! in a normal mode in response to an output signal STBi from the standby mode detection input buffer 31.
FIG. 4 is a circuit diagram of the bus input buffer 30 in FIG. 3. As shown in this drawing, the bus input buffer 30 is provided with a differential amplifier for receiving the bus signal BUS0:j! and a reference voltage Vref to perform a differential amplification operation. The differential amplifier is controlled in operation by the output signal STBi from the standby mode detection input buffer 31.